1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of data transfer for the semiconductor memory device. More specifically, it relates to a 2 port memory device containing a random access memory (RAM) port and a serial access memory (SAM) port and to a method of data transfer therefor.
2. Description of the Background Art
Recently, 2 port memory devices for application to graphic display systems have been proposed. Such a 2 port memory device comprises two ports, namely, a RAM port which can be accessed at random and a SAM port which can be serially accessed. The details of such device is disclosed in "Nikkei Electronics" Aug. 12, 1985 (p.211 to 240). A conventional method of data transfer between the RAM port and the SAM port is disclosed in, for example, Japanese Patent Laying-Open Gazette Number 242252/1987. These examples of the prior art will be described in the following.
FIG. 1 is a block diagram showing a schematic structure of a conventional 2 port memory device. Referring to the figure, the 2 port memory device comprises a RAM (Random Access Memory) 1, a SAM (Serial Access Memory) 2, a transfer portion 3 and a control circuit 4. The RAM 1 comprises a memory cell array 11, a row decoder 12, an I/O switch 13 and a column decoder 14. In the memory cell array 11, a plurality of word lines WL and a plurality of sets of bit line pairs BL and BL are arranged intersecting with each other, with memory cells MC provided at respective intersections. The row decoder 12 selects one word line out of the plurality of word lines WL based on an inputted row address. The I/O switch 13 is provided for respective bit lines BL and BL and is commonly connected to an I/O line 15. The column decoder 14 selects a desired bit line pair BL and BL by selectively opening/closing the I/O switch 13 based on an inputted column address. As is well known, in such a RAM 1, the writing and reading of data to and from an arbitrary memory cell MC can be carried out at random.
The transfer portion 3 is provided between the RAM 1 and the SAM 2 to transfer data between the RAM 1 and the SAM 2. The transfer portion 3 comprises precharging circuits 31, sense amplifiers 32 and transfer gates 33 each of which is provided for each bit line pair BL, BL. Each precharging circuit 31 precharges the corresponding bit line pair BL, BL in accordance with a precharging signal PR applied from a timing control circuit (not shown). Each sense amplifier 32 amplifies a small potential difference between the corresponding bit line pair BL, BL which appears in data reading or writing. These sense amplifiers 32 are activated by activating signals transmitted on a sense amplifier activating signal line pair SD, SD extending from the control circuit 4. Each transfer gate 33 controls opening/closing between the SAM 2 and the corresponding bit line pair BL, BL in response to a transfer signal TG applied thereto.
The SAM 2 comprises data registers 21 and a serial selector 22. A separate register 21 is provided for every bit line pair BL, BL to store data of one row of the memory cell array 11. The serial selector 22 reads the data held in the data register 21 to output the same serially to an input/output line 23 and writes serial data inputted through the input/output line 23 into the data register 21.
In the following, circuit structures of the transfer portion 3 and of the peripheral circuits in FIG. 1 will be described in detail with reference to FIG. 2. A memory cell MC.sub.0 is constituted by an N channel type MOS transistor (hereinafter referred as an NMOS transistor) NQ1 and a capacitor C and is selected by setting the corresponding word line WL at an H level. A precharging circuit 31.sub.0 is constituted by NMOS transistors NQ2 and NQ3 connected in series between the bit lines BL.sub.0 and BL.sub.0. A precharging signal PR is applied to the gate of each of the NMOS transistors NQ2 and NQ3 from a timing control circuit, not shown. The precharging circuit 31.sub.0 turns on when the precharging signal PR is at the H level, and it applies a precharging voltage Vcc/2 to the bit line pair BL.sub.0, BL.sub.0. Consequently, the bit line pair BL.sub.0, BL.sub.0 is precharged. A sense amplifiers 32.sub.0 comprises a pair of NMOS transistors NQ4 and NQ5 and a pair of P channel type MOS transistors (hereinafter referred to as PMOS transistors) PQ1 and PQ2, respectively cross coupled with each other. The sense amplifiers 320 amplifies a small potential difference between the bit line pair BL.sub.0 and BL.sub.0 as a pair of sense amplifier activating signal lines SD and SD from the control circuit 4 are set at the H level and L level, respectively. A transfer gate 33.sub.0 is constituted by two NMOS transistors NQ6 and NQ7 respectively connected between the bit line pair BL.sub.0, BL.sub.0 and a storage node pair DR.sub.0 and DR.sub.0 21.sub.0. These NMOS transistors NQ6 and NQ7 turn on when the transfer signal TG is at the H level to connect the bit line pair BL.sub.0, BL.sub.0 to the storage node pair DR.sub.0, DR.sub.0. The data register 21.sub.0 is constituted by two inverters IV1 and IV2 which are connected in parallel in opposite directions between the bit line pair BL.sub.0 and BL.sub.0.
The memory cell MC.sub.1, the precharging circuit 31.sub.1, the sense amplifiers 32.sub.1, the transfer gate 33.sub.1 and the data register 21.sub.1 have the same structure as the memory cell MC.sub.0, the precharging circuit 31.sub.0, the precharging circuit 31.sub.0, the sense amplifier 32.sub.0, the transfer gate 33.sub.0 and the data register 21.sub.0, respectively. Although two sets of memory cells, precharging circuits, sense amplifiers, transfer gates and the data registers are shown in FIG. 2 for the purpose of simplicity, there are a number of sets of these components as shown in FIG. 1, each of which has the same circuit structure as described above.
The control circuit 4 comprises two NMOS transistors NQ8 and NQ9 interposed in series between a pair of sense amplifier activating signal lines SD and SD, a PMOS transistor PQ3 interposed between the sense amplifier activating signal line SD and the power supply Vcc and an NMOS transistor NQ10 interposed between the sense amplifier activating signal line SD and the ground. A precharging signal PR is applied from a timing control circuit, not shown, to the base of each of the transistors NQ8 and NQ9. These NMOS transistors NQ8 and NQ9 turn on when the precharging signal PR is at the high level to apply a precharging voltage Vcc/2 to the pair of sense amplifier activating signal lines SD and SD. Consequently, the sense amplifier activating signal lines SD and SD are precharged. Sense amplifier enabling signals SAE and SAE are applied to the base of the PMOS transistor PQ3 and of the NMOS transistor NQ10 from a timing control circuit, not shown, respectively. The PMOS transistor PQ3 and the NMOS transistor NQ10 turn on when the sense amplifier enabling signals SAE and SAE are at the L level and H level, respectively, thereby driving the sense amplifier activating signal line SD to the H level and the sense amplifier activating signal line SD to the L level.
In the above described structure, the RAM 1 and the SAM 2 operate non-synchronously. The data of one row (one word line) stored in the memory cell array 11 are collectively transferred to the data register 21 of the SAM 2 by the transfer portion 3, and they are serially outputted through the input/output line 23 by means of the serial selector 22. The data inputted from the serial selector 22 are stored in the data register 21 and they are collectively transferred to the RAM 1 by the transfer portion 3 to be written in the memory cell array 11.
How the data is transferred from the RAM 1 to the SAM 2, for example from the memory cell MC.sub.0 to the data register 21.sub.0 will be described in the following with reference to the diagram of waveforms of FIG. 3. Prior to the data transfer, the precharging signal PR is at the H level, and the bit line pair BL.sub.0, BL.sub.0 and the sense amplifier activating signal line pair SD, SD are all precharged to Vcc/2. When the precharging signal PR is set at the L level at the time T.sub.0, the bit line pair BL.sub.0, BL.sub.0 and the sense amplifier activating signal line pair SD, SD are brought to a high impedance state while being maintained at the level of Vcc/2. Thereafter, when the word line WL is brought to the H level at the time T.sub.1, the charges stored in the capacitor C in the memory cell MC.sub.0 are read to the bit line BL.sub.0. Now, if the H level has been stored in the capacitor of the memory cell MC.sub.0, the potential on the bit line BL.sub.0 rises a little. After the time period of .DELTA.t.sub.1 long enough to enable full reading of the charges, that is, at the time t.sub.2, the sense amplifier enabling signals SAE and SAE are respectively set at the H level and the L level, whereby the sense amplifiers 32.sub.0 start amplification of the potential difference between the bit line pair BL.sub.0 and BL.sub.0. After the time period of .DELTA.t.sub.2 long enough to permit full amplification, namely, at the time t.sub.3, the transfer signal TG is brought to the H level. Since the driving capability of the inverters IV1 and IV2 constituting the data register 21.sub.0 is set smaller than the driving capability of each of the transistors constituting the sense amplifiers 32.sub.0, the data stored in the data register 21.sub.0 is rewritten by the sense amplifier 32.sub.0 through the transfer gate 33.sub.0. The data stored in the memory cell MC.sub.0 are transferred to the data register 21.sub.0 through the above described operation.
How the data is transferred from the SAM 2 to the RAM 1, for example from the data register 21.sub.0 to the memory cell MC.sub.0 will be described in the following with reference to the diagram of waveforms of FIG. 4. Prior to the data transfer, the precharging signal PR is set at the H level to precharge respective nodes. When the precharging signal PR is brought to the L level at the time t.sub.0 and thereafter the transfer signal TG is brought to the H level, the potentials on the bit line pair BL.sub.0 and BL.sub.0 gradually change in accordance with the data stored in the data register 21.sub.0. For example, if the storage node DR.sub.0 has been at the H level and the storage node DR.sub.0 has been at the L level, the bit line BL.sub.0 changes to the H level while the bit line BL.sub.0 changes to the L level. Thereafter, when the word line WL is brought to the H level at the time t.sub.1, the charges, namely, the information, stored in the capacitor of the memory cell MC.sub.0 are read on the bit line BL.sub.0. However, the information is offset by the driving capability of the data register 21.sub.0. After the potential difference between the bit line pair BL.sub.0, BL.sub.0 becomes large, the sense amplifier is activated at the time t.sub.2 to set the bit line BL.sub.0 at the L level and the bit line BL.sub.0 at the H level. On this occasion, the word line WL is at the H level, so that the data on the bit line BL.sub.0 are written in the memory cell MC.sub.0.
Although the sets of the memory cells and the data registers represented by reference characters with the suffix of 0 are employed in the foregoing, the data transfer is carried out in the same manner also in other sets.
Now, in a graphic display system, not all of the data but only a portion thereof is often transferred. FIGS. 5 and 6 show an example of a 2 port memory device enabling such partial transfer. The transfer gate 33.sub.0 is adapted to be controlled by a transfer signal TG.sub.0 while the transfer gate 33.sub.1 is adapted to be controlled by another transfer signal TG.sub.1. Partial transfer is carried out by setting only the transfer signal corresponding to the data register whose data is to be transferred at the H level. However, in the structure such as shown in FIGS. 5 and 6, the conventional method of transfer presents the following problems in data transfer from the data register 21 to the memory cell MC. The problem will be described in the following with reference to the diagram of waveforms of FIG. 7.
After the precharging signal PR is set at the L level at the time t0, the transfer signal TG.sub.0 becomes H level, and the transfer signal TG.sub.1 is maintained at the L level. At that time, the voltages on the bit line pair BL.sub.0, BL.sub.0 start changing in accordance with the data stored in the data register 21.sub.0. For example, assuming that the storage node DR.sub.0 is at the H level and the storage node DR.sub.0 is at the L level, the potential on the bit line BL.sub.0 rises from Vcc/2 while the potential on the bit line BL.sub.0 lowers from Vcc/2. When the potential of the bit line BL.sub.0 becomes higher than the threshold voltage of the NMOS transistor NQ5 constituting the sense amplifier 32.sub.0, the NMOS transistor NQ5 is brought to the on state. In the similar manner, when the potential of the bit line BL.sub.0 becomes lower than the threshold voltage of the PMOS transistor PQ1 constituting the sense amplifier 32.sub.0, the PMOS transistor PQ1 is brought to the on state. Consequently, the sense amplifier activating signal line SD is connected to the bit line BL.sub.0 and the sense amplifier activating signal line SD is connected to the bit line BL.sub.0. On this occasion, since the sense amplifier activating signal lines SD and SD are both at the high impedance state, the potential on the sense amplifier activating signal line SD gradually rises drawn by the bit line BL.sub.0 while the potential on the sense amplifier activating signal line SD gradually lowers drawn by the bit line BL.sub.0. When the potential on each of the sense amplifier activating signal lines SD and SD changes by an amount larger than the threshold voltage of the transistors constituting the sense amplifier 32.sub.1 from Vcc/2, the sense amplifier 32.sub.1 starts amplifying operation. However, at that time, the word line WL is not yet brought to the H level or, even when it is at the H level, the data of the memory cell MC.sub.1 are not yet fully read to the bit line pair BL.sub.1 and BL.sub.1, so that the sense amplifier 32 amplifies the data corresponding to the imbalance of itself.
Since the data transfer is carried out in the above described manner in the conventional 2-port memory device, when partial data transfer from the data register to the memory cell is carried out, the data stored in the memory cell which is not selected for the transfer may possibly be damaged (the data may possibly be inverted to an erroneous data).